1. Field
Embodiments of the present invention generally relate to methods for forming vertically stacked nanowires with desired materials on a semiconductor substrate, and more particularly to methods for forming vertically stacked nanowires on a semiconductor substrate with desired materials for fin field effect transistor (FinFET) semiconductor manufacturing applications.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. In particular, fin field effect transistors (FinFET) are often utilized to form three dimensional (3D) stacking of semiconductor chips. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow.
In manufacturing three dimensional (3D) stacked of semiconductor chips, multiple layers with different materials may be utilized to form nanowire structures to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices. However, using different materials to form the nanowire structures undesirably increases the manufacturing difficulty in integrating all these materials in the nanowire structures. Oftentimes, multiple complicated process sequences are required to complete the manufacturing processes for nanowire structures having more than one material, which may adversely cause high manufacturing costs, cycle times, and extra processing time. Furthermore, in the situations where different processing chambers are required to form each different film layers of the nanowire structures, transfer of the substrate in between different processing tools is always time consuming and sometime increases the likelihood of substrate contaminant when breaking vacuum between processing tools.
Thus, there is a need for improved methods for forming nanowire structures including the semiconductor fin structure with different materials on a substrate with good profile and dimension control for three dimensional (3D) stacking of semiconductor chips or other semiconductor devices.